1. Field of the Invention
The present invention relates to a semiconductor memory device using arbitrary data areas of a cache memory as data storage areas of a RAM(random access memory).
2. Prior Art
In recent years, microprocessors have raised operation clock frequencies and enlarged memory bandwidths. Therefore, the amount of data processed by microprocessors has become enormous. In particular, it has become necessary to access data of a substantial size rapidly as in image data.
In the case where both a cache memory allowing high-speed access to data and a RAM were required, hardware was conventionally constructed by preparing a cache memory 100 and a RAM 101 separately as shown in FIG. 1, for example. In such a case, the entire hardware increased. Especially in the case where the memories were mounted on a chip so as to be mixed with a microprocessor, the chip area of the microprocessor and the cost increased.
In order to avoid such an inconvenience, a part of the cache memory was used as the RAM in some semiconductor memory devices. In this cache memory, a status bit is set to a lock state when data are written into an entry used as the RAM. Data of the entry used as the RAM are thus prevented from being rewritten at the time of a cache miss. When such a technique was used, however, data rewriting control in a refill operation at the time of a cache miss became complicated and it was difficult to use large areas of the cache memory as the RAM.
Another example of a memory in which a part of the cache memory is used as the RAM is shown in FIG. 2. In FIG. 2, a control circuit 103 for controlling the input/output operation of stored data is provided for a single way or a plurality of ways of a data array 102, in a cache memory having a plurality of ways of set associative method so that the data array 102 of the cache memory is used as the RAM with treating the way as a unit.
Furthermore, according to an invention described in U.S. Pat. No. 5,410,669 (Apr. 25, 1995), some ways included in a plurality of ways of a cache memory can be used as a static RAM with treating the way as a unit.
In such a cache memory, the way is a unit when the data array of the cache memory is used as the RAM so that the capacity of the RAM is designed only by the way. Therefore, it is impossible to design the capacity of the RAM finely according to each system.
As heretofore described, the conventional techniques for constructing a memory having both a cache memory and a RAM had disadvantages of a large-sized configuration, complicated refill operation, and a RAM capacity which can not be arbitrarily designed.